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18 pcs
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18 pcs | On Request | 1 | On Request | On Request | 08+ | On Request | On Request |
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The Lattice LCMXO256C-3TN100C is a Complex Programmable Logic Device (CPLD) belonging to the MachXO family. Optimized for applications such as glue logic, bus bridging, and control logic, this device integrates features of both CPLDs and FPGAs.
Key specifications include 128 macro cells, with I/O pin counts ranging from 73 to 271. It operates across a flexible voltage range of 1.2V to 3.3V. The device offers embedded memory with up to 27.6 Kbits of sysMEM Embedded Block RAM and 7.7 Kbits of distributed RAM. It also features up to two analog PLLs for clock management.
This CPLD is supplied in a 100-pin TQFP package suitable for surface mounting. It supports standard interfaces like LVCMOS, LVTTL, PCI, and LVDS. The device is designed for non-volatile, infinitely reconfigurable operation, offering instant-on capability and excellent design security.
System-level support includes IEEE Standard 1149.1 Boundary Scan and IEEE 1532 compliant in-system programming. The MachXO series is known for its high I/O to logic density and support for density migration.
The Lattice LCMXO256C-3TN100C features 128 macro cells, 73 to 271 I/Os, and operates at 1.2V/1.5V/1.8V/2.5V/3.3V. It includes up to 27.6 Kbits of embedded RAM and 7.7 Kbits of distributed RAM.
The LCMXO256C-3TN100C is available in a 100-pin TQFP package.
Yes, the LCMXO256C-3TN100C is RoHS3 Compliant.
The Moisture Sensitivity Level (MSL) for the LCMXO256C-3TN100C is 1 Unlimited.
The LCMXO256C-3TN100C is REACH Unaffected.
MachXO devices are optimized for applications traditionally addressed by CPLDs and low capacity FPGAs, including glue logic, bus bridging, bus interfacing, power-up control, and control logic.