| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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6 pcs
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6 pcs | On Request | 1 | On Request | On Request | 04+ | On Request | On Request |
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The K4H511638B-TCB3 is a 536,870,912-bit double data rate synchronous DRAM from Samsung. Fabricated with high-performance CMOS technology, it achieves data rates up to 333Mb/s per pin due to its synchronous features with Data Strobe. This DRAM is organized as 4×8,388,608 words by 16 bits.
Key features include a double-data-rate architecture allowing two data transfers per clock cycle, bidirectional data strobe, and four banks of operation. All inputs, except data and DM, are sampled at the positive-going edge of the system clock. Data I/O transactions occur on both edges of the data strobe, with edge-aligned data output and center-aligned data input.
This component supports auto and self-refresh with a 7.8us refresh interval. It is supplied in a 66-pin TSOP II package. The operating voltage range is -0.5V to 3.6V, with VDD & VDDQ supply voltages between -1.0V and 3.6V relative to VSS. Power dissipation is rated at 1.5W, and short circuit current is 50mA.
The K4H511638B-TCB3 is suitable for various high-performance memory system applications requiring fast and efficient data transfer.
The voltage on any pin relative to VSS is -0.5V to 3.6V, and on VDD & VDDQ supply relative to VSS is -1.0V to 3.6V.
It is available in 66-pin TSOP and TSOP II packages.
The maximum data rate is 333Mb/s per pin.
The nominal power dissipation is 1.5W.
The storage temperature range is -55°C to 150°C.
The refresh interval is 7.8µs (8K/64ms refresh).
The maximum short circuit current is 50mA.