ISPPAC-CLK5610V-01TN48C

The Lattice Semiconductor ISPPAC-CLK5610V-01TN48C is an in-system programmable, zero-delay clock generator with universal fan-out buffer capabilities. It operates from 10MHz to 320MHz, offering low output-to-output skew of less than 50ps and low jitter peak-to-peak of less than 60ps.

This device supports up to 20 programmable fan-out buffers with configurable output standards including LVTTL, LVCMOS, HSTL, SSTL, LVDS, and LVPECL. It features a fully integrated high-performance PLL with programmable lock detect and on-chip loop filter. The output impedance is programmable from 40 to 70 Ohms in 5 Ohm increments, and slew rate is also programmable. The device supports up to 10 banks with individual VCCO and GND, operating from 1.5V to 3.3V.

It offers precision programmable phase adjustment per output with up to +/- 12ns skew range and supports up to five clock frequency domains. Flexible clock reference and external feedback inputs are available with programmable input standards. The device includes four user-programmable profiles stored in E2CMOS memory for test and multiple operating configurations, along with full JTAG boundary scan test and in-system programming support.

The ISPPAC-CLK5610V-01TN48C is available in a 48-TQFP package and operates within a commercial temperature range of 0°C to 70°C. Its applications include circuit board common clock generation and distribution, PLL-based frequency generation, and high fan-out or zero-delay clock buffering.