| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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3,000 pcs
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3000 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Differential | |
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| PLL | |
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The Lattice Semiconductor ISPPAC-CLK5304S-01TN48C is an in-system-programmable zero-delay universal fan-out buffer designed for clock distribution applications. It supports input/output frequencies ranging from 8MHz to 267MHz, featuring low output-to-output skew of less than 100ps and peak-to-peak jitter below 70 ps.
This device offers up to 20 programmable fan-out buffers with support for various single-ended output standards including LVTTL, LVCMOS, HSTL, eHSTL, and SSTL. It also provides programmable output impedance from 40 to 70 Ω in 5 Ω increments and programmable slew rate. The buffer operates with a supply voltage between 3V and 3.6V and is available in a 48-TQFP package.
Key features include a fully integrated high-performance PLL with programmable lock detect and on-chip loop filter, compatible with spread spectrum clocks. It offers precision programmable phase adjustment per output with 8 settings and up to +/- 5ns skew range. The device supports up to three clock frequency domains and features flexible clock reference and external feedback inputs with programmable termination.
The ISPPAC-CLK5304S-01TN48C is suitable for circuit board common clock distribution, PLL-based frequency generation, and high fan-out clock buffering applications. It is designed for surface mount installation and operates within a commercial temperature range of 0°C to 70°C.
The operating voltage range is 3V to 3.6V.
The operating temperature range is 0°C to 70°C.
It is available in a 48-TQFP (7x7) package for surface mounting.
Supported input standards include HSTL, LVCMOS, LVDS, LVPECL, LVTTL, and SSTL. Supported output standards are eHSTL, HSTL, LVCMOS, LVTTL, and SSTL.
The maximum operating frequency is 267MHz.
Yes, it features a PLL with bypass capability.