| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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96 pcs
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96 pcs | On Request | 1 | On Request | On Request | 1116 | On Request | On Request |
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| Manufacturer Name | |
| AEC Qualified | |
| Automotive Grade | |
| Industrial Grade | |
| Medical Grade | |
| Military Grade | |
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| Tape & Reel |
The Lattice Semiconductor ISPLSI2128A-80LT176 is part of the ispLSI 2000 family of CPLDs, designed for high-performance system logic needs. This device implements logic functions ranging from registers and counters to multiplexers and complex state machines.
With a system performance of 300 MHz and a pin-to-pin delay of 3.0 ns, the ISPLSI2128A-80LT176 provides efficient logic implementation. It features a 5V programmable logic core and user-selectable 3.3V or 5V I/O options, offering flexibility for various system designs. The device supports in-system programmability via ispJTAG (IEEE 1149.1) and includes boundary scan test capabilities.
This CPLD family offers densities ranging from 1,000 to 8,000 gates, with devices containing multiple Generic Logic Blocks (GLBs) for system flexibility. A balanced ratio of registers and I/O cells optimizes internal logic and external connections, supported by a global interconnect scheme that allows up to 80% utilization of available logic.
The ISPLSI2128A-80LT176 is supplied in a 176-TQFP package, suitable for surface mounting.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The system performance is 300 MHz.
The pin-to-pin delay is 3.0 ns.
It supports 3.3V/5V compatible I/O.
The programmable logic core voltage is 5V.
It is in-system programmable via ispJTAG using IEEE 1149.1 (JTAG).
Yes, it supports boundary scan test according to IEEE 1149.1.
It features programmable open-drain outputs.