| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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27 pcs
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27 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
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27 pcs
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27 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Lattice Semiconductor ispLSI 1000 Family CPLD, specifically the ISPLSI1032E-125LTN, is a high-density programmable logic device designed for flexible system implementation. This CPLD features 384 registers and 128 universal I/O pins, supported by five dedicated clock input pins. It operates at a maximum frequency of 90 MHz with a propagation delay of 12 ns.
Built with high-performance CMOS technology, this device offers 11000 PLD gates and a global routing pool for complete inter-connectivity. It is 5V in-system programmable using Lattice ISP or Boundary Scan Test (IEEE 1149.1) protocols, facilitating easier debugging and faster time-to-market. The CPLD supports both synchronous and asynchronous clocks and includes features like programmable output slew rate control to minimize switching noise.
This device is suitable for combining glue logic and structured designs, offering enhanced pin-locking capabilities. The ispLSI 1000 family is designed to provide the ease of use and fast system speed of PLDs with the density and flexibility of Field Programmable Gate Arrays (FPGAs).
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The maximum operating frequency is 90 MHz.
The propagation delay is 12 ns.
It has 128 universal I/O pins.
The device contains 384 registers.
It has 11000 PLD gates.
There are five dedicated clock input pins.
The device is 5V in-system programmable.