EPM7128EQC100-12
Altera
The Altera EPM7128EQC100-12 is a high-performance CPLD from the MAX 7000 family. It features 128 macrocells and operates at a 5V supply voltage.
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286 pcs
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286 pcs | On Request | 1 | On Request | On Request | 426 | On Request | On Request |
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The Lattice Semiconductor ISPLSI1032-80LT is a high-density programmable logic device (CPLD) belonging to the ispLSI 1000 family. This device is built using high-performance E2CMOS technology, enabling a maximum operating frequency of 90 MHz and a propagation delay of 12 ns.
Key features include 384 registers and 128 universal I/O pins, supported by five dedicated clock input pins. The CPLD architecture incorporates a Global Routing Pool (GRP) for complete inter-connectivity between logic elements. It operates at a 5V in-system programmable voltage and is designed for applications requiring glue logic and structured designs.
This device is in-system programmable using Lattice ISP or Boundary Scan Test (IEEE 1149.1) protocols. It is 100% tested at the time of manufacture and offers TTL compatible inputs and outputs. The ispLSI 1000 family provides the ease of use and fast system speed of PLDs with the density and flexibility of FPGAs.
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Estimated market price range - modelled values for guidance only, not live distributor offers.
The maximum operating frequency is 90 MHz.
The propagation delay is 12 ns.
The device contains 384 registers.
There are 128 universal I/O pins.
The device is 5V in-system programmable.
The RoHS status is RoHS3 Compliant.
The Moisture Sensitivity Level is 1 Unlimited.