| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
117 pcs
|
117 pcs | On Request | 1 | On Request | On Request | 11+ | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Delay Time tpd(1) Max | |
| Lead Spacing | |
| Mounting Type | |
| Number of Gates | |
| Number of I | |
| Number of Logic Elements | |
| Number of Macrocells | |
| Operating Temperature | |
| Programmable Type | |
| Supplier Device Package | |
| Supplier Package | |
| Voltage Supply |
The Lattice Semiconductor ISPLSI 5512VA-110LB388 is a high-density, 3.3V In-System Programmable CPLD based on E2CMOS technology. It features 512 macrocells, 24000 PLD gates, and up to 288 I/O pins, supporting a 3.3V power supply and user-selectable 3.3V/2.5V I/O.
This device boasts a maximum operating frequency of 110 MHz and a propagation delay of 8.5 ns. Its architecture includes a SuperWIDE 32 Generic Logic Block (GLB) size for optimal performance and SuperWIDE Input Gating with 68 inputs for fast counters and state machines. It is also 100% IEEE 1149.1 boundary scan testable.
The ISPLSI 5512VA-110LB388 is housed in a PCB-efficient 388-BGA package, suitable for surface mounting. It operates within a temperature range of 0°C to 70°C (TA). This CPLD is designed for increased manufacturing yields and reduced time-to-market, allowing for reprogramming of soldered devices for faster debugging.
The maximum operating frequency is 110 MHz.
The maximum propagation delay is 8.5 ns.
It has 512 macrocells.
The voltage supply range is 3V to 3.6V.
It is supplied in a 388-BGA (35x35) package, specifically a 388-BBGA, and is surface mountable.
The operating temperature range is 0°C to 70°C (TA).