ISPLSI 5256VE-80LF256

The Lattice Semiconductor ISPLSI5256VE-80LF256 is a Second Generation SuperWIDE High Density In-System Programmable Logic Device. It offers 12000 PLD Gates and 256 Macrocells, with up to 144 I/O Pins and 256 Registers. This device operates with a 3.3V power supply and supports user-selectable 3.3V/2.5V I/O.

Featuring high-speed global interconnect and a SuperWIDE Generic Logic Block, it achieves a maximum operating frequency of 165 MHz and a propagation delay of 6.0 ns. The device is built using E2 CMOS technology and is TTL/3.3V/2.5V compatible. It is electrically erasable, reprogrammable, and non-volatile, allowing for programmable speed/power logic path optimization.

The ISPLSI5256VE-80LF256 is designed for in-system programmability, which increases manufacturing yields and reduces time-to-market. It is also 100% IEEE 1149.1 boundary scan testable. The component comes in a PCB-efficient Ball Grid Array (BGA) package, specifically FPBGA-208-44, and interfaces with standard 5V TTL devices.

Key architectural features include an enhanced pin-locking architecture, a single-level global routing pool, and SuperWIDE GLBs. The wrap-around product term sharing array supports up to 35 product terms per macrocell. Macrocells support concurrent combinatorial and registered functions, with registers featuring multiple control options like Set, Reset, and Clock Enable. The device includes four dedicated clock input pins plus macrocell product term clocks. Programmable I/O supports options such as Bus-Hold, Pull-up, Open Drain, and Slew Rate control.