| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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762 pcs
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762 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Delay Time tpd(1) Max | |
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| Programmable Type | |
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| Tape & Reel | |
| Voltage Supply |
The Lattice Semiconductor ISPLSI 5256VE-100LF256 is an In-System Programmable (ISP) 3.3V SuperWIDE High Density PLD. It features 12000 PLD gates and 256 macrocells, providing significant logic capacity for complex designs.
This CPLD supports up to 144 I/O pins and offers a maximum operating frequency of 165 MHz with a propagation delay of 6.0 ns. It operates on a 3.3V power supply and is user-selectable for 3.3V/2.5V I/O. The device utilizes E2CMOS technology, making it electrically erasable and reprogrammable.
Designed for high performance, the ispLSI 5256VE family incorporates a SuperWIDE Generic Logic Block (GLB) and a Global Routing Pool (GRP) for efficient interconnections. It is suitable for applications requiring fast counters, state machines, and address decoders. The device is available in a PCB-efficient Ball Grid Array (BGA) package.
The ISPLSI 5256VE-100LF256 is mounted using a surface mount technique and comes in a 256-BGA package, specifically a 256-FPBGA (17x17). It operates within a temperature range of 0°C to 70°C (TA).
The maximum operating frequency is 165 MHz.
The propagation delay is a maximum of 6.0 ns.
It has 256 macrocells.
The voltage supply is between 3V and 3.6V.
The operating temperature is from 0°C to 70°C (TA).
It is supplied in a 256-FPBGA (17x17) package.