| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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330 pcs
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330 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Tape & Reel | |
| Voltage Supply |
The Lattice Semiconductor ISPLSI 2064VE-200LTN100 is a 3.3V In-System Programmable (ISP) High Density SuperFAST™ CPLD. It offers 2000 PLD gates and 64 macrocells, with a maximum operating frequency of 280MHz and a propagation delay of 3.5ns. This device is designed for high-performance applications requiring fast counters, state machines, and address decoders.
The ispLSI 2064VE architecture is based on E2CMOS® technology, providing non-volatile, electrically erasable, and reprogrammable logic. It supports standard 5V TTL device interfaces and features 64 I/O pins. The device is available in a 100-TQFP (14x14) package and is surface mountable.
Key features include in-system programmability via Boundary Scan Test Access Port (TAP), synchronous and asynchronous clocks, and programmable output slew rate control. The device is also 100% IEEE 1149.1 Boundary Scan Testable, enhancing manufacturing yields and product quality. It is suitable for applications demanding the density and flexibility of FPGAs with the ease of use and speed of PLDs.
The maximum operating frequency is 280MHz.
The propagation delay is 3.5ns.
The supply voltage ranges from 3V to 3.6V.
There are 64 macrocells available.
It is supplied in a 100-TQFP (14x14) package.
The operating temperature range is 0°C to 70°C (TA).