| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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1,000 pcs
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1000 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
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25 pcs
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25 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Integrated Silicon Solution IS43R16320D-6BLI is a high-speed 512Mbit DDR SDRAM designed for demanding applications. It utilizes a double-data-rate architecture, enabling two data transfers per clock cycle for enhanced performance.
Key electrical specifications include a clock frequency of 166 MHz, an access time of 700 ps, and a write cycle time of 15 ns. The device operates within a voltage range of 2.3V to 2.7V and supports SSTL_2 compatible I/O. It offers programmable features such as burst length (2, 4, 8), burst type (Sequential and Interleave), and CAS latency (2, 2.5, 3).
This DRAM is organized as 32M x 16 and is housed in a 60-TFBGA (8x13) package, suitable for surface mounting. The operating temperature range is -40°C to 85°C.
The device supports Auto Refresh and Self Refresh modes, along with Auto Precharge. It is designed for concurrent operation with four internal banks. The lead-free package and industrial operating temperature range make it suitable for various electronic systems.
| Qty | Low | High |
|---|---|---|
| 1+ | $1.28 | $1.28 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The memory size is 512 Mbit, organized as 32M words by 16 bits.
The general operating voltage range is 2.3V to 2.7V. Specific speed grades require 2.5V ± 0.2V (for -6) and 2.6V ± 0.1V (for -5).
The device supports a clock frequency of 166 MHz.
The IS43R16320D-6BLI is packaged in a 60-ball TFBGA (8x13mm) for surface mount.
The industrial temperature range is -40°C to +85°C. Commercial (0°C to +70°C) and automotive (-40°C to +105°C) variants are also available.
It uses SSTL_2 compatible I/O signaling.
Burst lengths of 2, 4, and 8 are supported, in both sequential and interleave burst order.