A3PE600-PQG208
Microchip Technology
The Microchip Technology A3PE600-PQG208 is a Field Programmable Gate Array (FPGA) from the ProASIC3E series. It features 147 I/O pins and 600,000 gates.
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1,540 pcs
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1540 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
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3 pcs
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3 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Agilent Technologies HDMP-1022 is a low-cost Gigabit rate transmit/receive chip set designed for point-to-point data links. It functions as a virtual ribbon cable replacement, handling all complexity of encoding, multiplexing, clock extraction, and decoding.
This chip set supports a user-selectable serial data rate ranging from 150 to 1500 MBaud. The parallel data interface is 16 or 20 bits wide with standard TTL logic levels. A flag bit can be utilized as an additional bit or for frame indication. The device includes an on-chip state machine for automatic link management and an on-chip PLL for frame synchronization.
Implemented in a low-cost Aluminum M-Quad 80 package, the HDMP-1022 operates within a temperature range of 0°C to 85°C. Its applications include backplane serialization, bus extension, video and image acquisition, and implementing standards like SCI-FI and Serial HIPPI.
The chip set hides complex serial communication protocols from the user, allowing for the transmission of arbitrary data without restriction. The receiver chip includes a state-machine controller for startup handshake protocol in duplex link configurations.
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| 1+ | $0.99 | $0.99 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The serial data rate is user selectable and ranges from 150 to 1500 MBaud.
The parallel data interface is 16 or 20 bits wide, with an option for a flag bit making it 17 or 21 bits.
The operating temperature range is 0°C to 85°C.
The HDMP-1022 is available in an Aluminum M-Quad 80 package and a QFP package.