| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
30 pcs
|
30 pcs | On Request | 1 | On Request | On Request | 02+ | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Propagation Delay | |
| SVHC Present |
The GAL20V8A15QP from Lattice Semiconductor is a high-performance Electrically-Erasable Programmable Logic Device (PLD) utilizing E2CMOS technology. It features a maximum propagation delay of 5ns and a maximum clock frequency (Fmax) of 166MHz. The device also offers a maximum clock to data output delay of 4ns.
Designed for flexibility, the GAL20V8A15QP has eight Output Logic Macrocells (OLMCs) that can be configured by the user, allowing it to emulate various PAL architectures with full function, fuse map, and parametric compatibility. It supports 100 erase/write cycles and provides over 20 years of data retention.
This PLD is housed in a DIP-24 package. It includes features such as active pull-ups on all pins and preload and power-on reset for all registers, ensuring 100% functional testability. Applications include DMA control, state machine control, and high-speed graphics processing.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The GAL20V8A15QP comes in a DIP-24 (24-pin Dual In-line Package).
The maximum propagation delay is 5 ns.
The maximum clock frequency is 166 MHz.
The maximum clock to data output delay is 4 ns.
The device supports a minimum of 100 erase/write cycles.
Data retention is in excess of 20 years.
The typical supply current is 75 mA for the low power device and 45 mA for the quarter power device.