| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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164 pcs
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164 pcs | On Request | 1 | On Request | On Request | 9135 | On Request | On Request | |
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16 pcs
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16 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Lattice Semiconductor GAL16V8A-10LP is a high-performance Electrically Erasable CMOS (E2CMOS) Programmable Logic Device (PLD) from the GAL Family. It combines high speed with the flexibility of E2 technology, allowing for quick and efficient reprogramming. This device features 8 macro cells, providing significant design flexibility for complex logic configurations.
Key electrical specifications include a maximum propagation delay of 3.5 ns and an Fmax of 250 MHz. It operates at a nominal voltage of 5V. The GAL16V8A-10LP utilizes UltraMOS Advanced CMOS Technology and offers power reduction compared to bipolar devices, with typical Icc values of 75mA for low power and 45mA for quarter power modes. Active pull-ups are present on all pins.
The device supports 100 erase/write cycles with data retention exceeding 20 years. It is packaged in a 20-pin PDIP. The GAL16V8A-10LP is designed to emulate various 20-pin PAL architectures with full functional compatibility. It is suitable for applications requiring standard logic speed upgrades, DMA control, and state machine control.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The nominal operating voltage is 5V.
The device is available in a PDIP-20 package.
The maximum clock frequency (Fmax) is 250 MHz.
The maximum propagation delay is 3.5 ns.
It has 8 macro cells.
Data retention is 20 years.
The erase time is less than 100 ms.