| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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2,011 pcs
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2011 pcs | On Request | 1 | On Request | On Request | 24+ | On Request | On Request | |
|
240 pcs
|
240 pcs | On Request | 1 | On Request | On Request | 08+ | On Request | On Request |
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The Altera EPM9560RI304-20 is a register-rich CMOS programmable logic device (PLD) belonging to the MAX 9000 family. This CPLD offers a density of 12K gates and 560 macro cells, operating at a maximum frequency of 100MHz with a 5V core voltage.
Key features include MultiVolt I/O interface compatibility with 5.0V and 3.3V logic levels, and compliance with the PCI SIG PCI Local Bus Specification, Revision 2.2. It also incorporates JTAG boundary-scan test circuitry compliant with IEEE Std. 1149.1-1990.
The device is housed in a 304-pin RQFP package. Its flexible interconnect structure, including FastTrack Interconnect, provides fast and predictable routing delays. Programmable output slew-rate control helps reduce switching noise.
This CPLD is suitable for applications requiring digital signal processing, wide-data-path manipulation, bus interfaces, TTL integration, and high-speed controllers.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The EPM9560RI304-20 CPLD has 12K gates.
The EPM9560RI304-20 has 560 macro cells.
The maximum operating frequency for the EPM9560RI304-20 is 100MHz.
The EPM9560RI304-20 operates at 5V.
The EPM9560RI304-20 is supplied in a 304-pin RQFP package.
Yes, the EPM9560RI304-20 features a MultiVolt I/O interface, enabling the device core to run at 5.0 V while I/O pins are compatible with 5.0-V and 3.3-V logic levels.
Yes, the EPM9560RI304-20 is fully compliant with the PCI SIG PCI Local Bus Specification, Revision 2.2 for 5.0-V operation.