AT27C256R-70JU-T
MIC
The Microchip Technology AT27C256R-70JU-T is a 256 Kbit One-Time Programmable Read-Only Memory with a 70ns access time and 5V operating voltage. It is available in a surface mountable package.
| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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1,523 pcs
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1523 pcs | On Request | 1 | On Request | On Request | 15+11+ | On Request | On Request |
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The Altera MAX 9000 family, including the EPM9320ALI84-10, consists of high-performance CMOS EEPROM-based programmable logic devices (PLDs). Built on a third-generation Multiple Array MatriX (MAX®) architecture, these devices offer densities ranging from 6,000 to 12,000 usable gates.
The EPM9320ALI84-10 features 6,000 usable gates, 484 flipflops, and 320 macrocells. It provides a pin-to-pin logic delay of 10 ns and a maximum counter frequency of 144 MHz. The device supports 5.0-V in-system programmability (ISP) via an IEEE Std. 1149.1 JTAG interface and is compliant with the PCI Local Bus Specification, Revision 2.2.
Additional features include MultiVolt™ I/O interface operation, allowing interfacing with 3.3-V and 5.0-V devices, and programmable output slew-rate control to reduce switching noise. The device is offered in an 84-pin PLCC package, suitable for surface mounting.
This PLD family is supported by Altera's MAX+PLUS II development system and interfaces with various EDA tools. It is designed for applications requiring high-density, high-performance programmable logic.
| Qty | Low | High |
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| 1+ | $2.50 | $2.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The pin-to-pin logic delay is 10 ns.
The maximum counter frequency is 144 MHz.
The device has 6,000 usable gates.
It supports both 3.3-V and 5.0-V devices.
Yes, it features 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface.
It is supplied in an 84-PLCC package.