| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
8,000 pcs
|
8000 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Delay Time tpd(1) Max | |
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| Voltage Supply |
The Intel EPM7512AETC144-7N is a Complex Programmable Logic Device (CPLD) from the MAX 7000A family, built on a second-generation Multiple Array MatriX (MAX) architecture. This 3.3V device offers high performance with a pin-to-pin logic delay of 4.5 ns and counter frequencies up to 227.3 MHz.
Key features include 512 macrocells, 120 I/O pins, and 10,000 gates. It supports in-system programmability (ISP) via an IEEE 1149.1 JTAG interface and is compliant with IEEE Std. 1532. The MultiVolt I/O interface allows the core to run at 3.3V while supporting 5.0V, 3.3V, and 2.5V logic levels.
This CPLD is supplied in a 144-TQFP (20x20) package and is designed for surface mounting. It operates within an extended temperature range of 0°C to 70°C (TA). The device also supports hot-socketing, making it suitable for various embedded applications requiring flexible logic implementation.
The maximum propagation delay for the EPM7512AETC144-7N is 7.5 ns.
The EPM7512AETC144-7N operates with a supply voltage range of 3V to 3.6V.
The operating temperature range for the EPM7512AETC144-7N is 0°C to 70°C (TA).
The EPM7512AETC144-7N is supplied in a 144-TQFP (20x20) package.
Yes, the EPM7512AETC144-7N supports in-system programmability (ISP) through an IEEE 1149.1 JTAG interface.
The Moisture Sensitivity Level (MSL) for the EPM7512AETC144-7N is 1.