| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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10 pcs
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10 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
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7 pcs
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7 pcs | On Request | 1 | On Request | On Request | 2026-02-25 06:16:38 | On Request | On Request |
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| Manufacturer Name | |
| SVHC Present |
The Altera EPM7256SRC20812 is a Complex Programmable Logic Device (CPLD) belonging to the MAX 7000S family, built on Altera's second-generation MAX architecture. Fabricated with advanced CMOS technology, this EEPROM-based PLD operates with a 2.5-V supply voltage. It provides 5K usable gates and 256 macro cells, with pin-to-pin delays as fast as 3.5 ns and counter speeds up to 303.0 MHz.
This device is pin-compatible with the 5.0-V MAX 7000S and 3.3-V MAX 7000A device families. It supports advanced 2.5-V in-system programmability (ISP) through the IEEE Std. 1149.1 JTAG interface. The EPM7256SRC20812 comes in a 208-pin PQFP package.
Designed for high-density and high-performance applications, the MAX 7000S family offers a balance of speed, density, and power efficiency. Its ISP capabilities allow for efficient in-system programming and updates, making it suitable for various embedded system designs.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The EPM7256SRC20812 operates at a nominal voltage of 2.5V.
The EPM7256SRC20812 has 256 macro cells.
The maximum counter frequency for the EPM7256SRC20812 is 303.0 MHz.
The EPM7256SRC20812 is supplied in a PQFP-208 package.