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1 pcs
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1 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Altera EPM7256EGM883B-20 is a high-density, high-performance CPLD based on Altera's second-generation MAX architecture. Fabricated with advanced CMOS technology, this EEPROM-based device offers up to 5,000 usable gates, in-system programmability (ISP), pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.
This CPLD supports 5.0-V in-system programmability through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. It also includes built-in JTAG boundary-scan test (BST) circuitry. The device is housed in a PGA package.
The MAX 7000 family devices, including the EPM7256EGM883B-20, are suitable for various digital logic applications requiring programmable solutions. Their performance characteristics make them a viable option for designs needing fast logic implementation and in-system configuration.
| Qty | Low | High |
|---|---|---|
| 1+ | $2.50 | $2.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The package type for the EPM7256EGM883B-20 is PGA.
The RoHS status is RoHS3 Compliant.
The MSL is 1 Unlimited.
The REACH status is REACH Unaffected.
The EPM7256EGM883B-20 has 5,000 usable gates.
The pin-to-pin delay is as fast as 5 ns.
The counter speed is up to 175.4 MHz.