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1 pcs
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1 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Altera EPM7256ATI144-10 is a high-density, high-performance CPLD based on the second-generation MAX architecture. Fabricated with advanced CMOS technology, this EEPROM-based device operates with a 3.3-V supply voltage.
Key specifications include 5K usable gates, 256 macro cells, and a maximum operating frequency of 93.5 MHz. It features a fast pin-to-pin delay of 4.5 ns and a counter speed of up to 227.3 MHz. The device is housed in a 144-pin TQFP package.
This CPLD supports 3.3-V in-system programmability (ISP) through an IEEE Std. 1149.1 JTAG interface. It also includes built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1 and supports JEDEC Jam STAPL (JESD-71).
The EPM7256ATI144-10 is suitable for various embedded applications requiring programmable logic. Its pin compatibility with 5.0-V MAX 7000S devices offers design flexibility.
| Qty | Low | High |
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| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The EPM7256ATI144-10 operates at a 3.3V supply voltage.
The EPM7256ATI144-10 is available in a 144-pin TQFP package.
The EPM7256ATI144-10 has a maximum operating frequency of 93.5 MHz.
The pin-to-pin delay for the EPM7256ATI144-10 is as fast as 4.5 ns.
The EPM7256ATI144-10 offers up to 10,000 usable gates.
Yes, the EPM7256ATI144-10 supports 3.3-V in-system programmability (ISP) through the IEEE Std. 1149.1 JTAG interface.