| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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6,000 pcs
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6000 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Delay Time tpd(1) Max | |
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| Tape & Reel | |
| Voltage Supply |
The Intel EPM7256AETC144-5 is a high-performance, 3.3-V EEPROM-based programmable logic device (PLD) from the MAX 7000A family. Built on a second-generation Multiple Array MatriX (MAX) architecture, this CPLD offers 256 macrocells and 16 logic elements, with a total of 5000 usable gates. It provides 120 I/O pins and a fast pin-to-pin propagation delay of 5.5 ns.
Designed for in-system programmability (ISP) via an IEEE Std. 1149.1 JTAG interface, the EPM7256AETC144-5 supports advanced pin-locking capabilities and is compliant with IEEE Std. 1532. The device operates within a temperature range of 0°C to 70°C (TA) and requires a supply voltage between 3V and 3.6V. Its MultiVolt I/O interface allows the core to run at 3.3V while supporting 5.0-V, 3.3-V, and 2.5-V logic levels.
This CPLD comes in a 144-TQFP (20x20) surface mount package, specifically the 144-LQFP variant. It is suitable for applications requiring flexible logic implementation and in-system configuration.
The maximum propagation delay for the EPM7256AETC144-5 is 5.5 ns.
The EPM7256AETC144-5 has 256 macrocells.
The supply voltage for the EPM7256AETC144-5 ranges from 3V to 3.6V.
The operating temperature range is 0°C to 70°C (TA).
The EPM7256AETC144-5 is supplied in a 144-LQFP package.
The RoHS status is RoHS3 Compliant.
The Moisture Sensitivity Level is 1 Unlimited.