| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
3,120 pcs
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3120 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Delay Time tpd(1) Max | |
| Lead Spacing | |
| Mounting Type | |
| Number of Gates | |
| Number of I | |
| Number of Logic Elements | |
| Number of Macrocells | |
| Operating Temperature | |
| Programmable Type | |
| Supplier Device Package | |
| Tape & Reel | |
| Voltage Supply |
The Intel EPM7256AETC100-5N is a high-performance, 3.3-V EEPROM-based programmable logic device (PLD) from the MAX 7000A family. Built on a second-generation Multiple Array MatriX (MAX) architecture, this CPLD offers 256 macrocells and 5000 gates, with a maximum pin-to-pin delay of 5.5 ns. It supports in-system programmability (ISP) via an IEEE 1149.1 JTAG interface.
This device features a MultiVolt I/O interface, allowing its core to run at 3.3 V while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels. The EPM7256AETC100-5N is supplied in a 100-TQFP package, designed for surface mounting. It operates within a temperature range of 0°C to 70°C (TA).
Key features include a bus-friendly architecture with programmable slew-rate control and an open-drain output option. The device also incorporates programmable macrocell registers with individual control options and a programmable power-saving mode for reduced power consumption. Its pin count is 84 I/O pins.
The maximum propagation delay is 5.5 ns.
It has 256 macrocells.
The operating voltage is between 3V and 3.6V.
It is supplied in a 100-TQFP package.
The operating temperature range is 0°C to 70°C.