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646 pcs
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646 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Altera MAX 7000 family CPLD, part number EPM7192SQ1160-10, is based on Altera's second-generation MAX architecture and fabricated with advanced CMOS technology. This EEPROM-based device provides 600 to 5,000 usable gates, offering significant logic capacity for various applications.
Key electrical characteristics include a fast pin-to-pin delay of 5 ns and counter speeds up to 175.4 MHz, enabling high-performance designs. It supports 5.0-V in-system programmability (ISP) through an IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface, with ISP circuitry compatible with IEEE Std. 1532. The device also features built-in JTAG boundary-scan test (BST) circuitry.
Packaged in a QFP form factor, the EPM7192SQ1160-10 is suitable for board-level integration. Its design considerations include the need for appropriate power supply and programming interfaces to leverage its in-system programmability and high-speed logic capabilities.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The pin-to-pin delay is as fast as 5 ns.
The maximum counter speed is up to 175.4 MHz.
The device provides 128 or more macrocells.
Yes, it supports 5.0-V in-system programmability (ISP).
It is available in a QFP (quad flat pack) package.
It uses IEEE Std. 1149.1 JTAG interface and is compatible with IEEE Std. 1532 ISP circuitry.
It belongs to the Altera MAX 7000 CPLD family.