| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
2,150 pcs
|
2150 pcs | On Request | 1 | On Request | On Request | 24+ | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Architecture | |
| Halogen Free | |
| Lead Spacing | |
| Lead Style | |
| Mounting Type | |
| SVHC Present | |
| Technology |
The Altera MAX 7000 CPLD family, including the EPM7128STC100-6, is based on Altera's second-generation MAX architecture. Fabricated with advanced CMOS technology, these EEPROM-based devices provide up to 5,000 usable gates, In-System Programmability (ISP), pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.
The EPM7128STC100-6 is designed for high-performance applications requiring flexible logic implementation. Its surface mount package is suitable for various board designs.
This CPLD is part of a family known for its reliability and performance in embedded systems. The MAX 7000 series offers a balance of density, speed, and power consumption.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The EPM7128STC100-6 is packaged in a 100-TQFP and is surface mount.
It has 5000 usable gates.
The maximum pin-to-pin delay is 5 ns.
The maximum counter speed is 175.4 MHz.
Yes, the EPM7128STC100-6 supports in-system programming (ISP).
The architecture is MAX.