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4 pcs
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4 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Altera EPM7128S-15ES is a Complex Programmable Logic Device (CPLD) belonging to the MAX 7000 family. Based on Altera's second-generation MAX architecture and fabricated with advanced CMOS technology, this EEPROM-based device provides a density range of 600 to 5,000 usable gates.
Key electrical specifications include pin-to-pin delays as fast as 5 ns and counter speeds up to 175.4 MHz. It supports 5.0-V in-system programmability (ISP) through an IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface, with ISP circuitry compatible with IEEE Std. 1532. The device also features built-in JTAG boundary-scan test (BST) circuitry.
Packaged in a QFP form factor, the EPM7128S-15ES is suitable for various embedded applications requiring flexible logic implementation. Its design emphasizes high performance and in-system configurability.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The pin-to-pin delay is as fast as 5 ns.
The counter speed is up to 175.4 MHz.
Yes, it supports 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface.
The EPM7128S-15ES is available in a QFP package.