| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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16 pcs
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16 pcs | On Request | 1 | On Request | On Request | 97 | On Request | On Request |
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The Altera EPM7128EQI100-20 is a member of the MAX 7000 family of high-density, high-performance Programmable Logic Devices (PLDs). Based on Altera’s second-generation MAX architecture and fabricated with advanced CMOS technology, this EEPROM-based device provides a versatile solution for various digital logic applications.
Key electrical characteristics include a range of 600 to 5,000 usable gates, enabling complex logic implementations. It boasts pin-to-pin delays as fast as 5 ns and counter speeds up to 175.4 MHz, ensuring high-speed operation. The device supports 5.0-V in-system programmability (ISP) via an IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface, facilitating easy design updates and testing.
This PLD features built-in JTAG boundary-scan test (BST) circuitry, enhancing testability. It is supplied in a QFP package, suitable for surface mounting. The MAX 7000 family, including devices like the EPM7128EQI100-20, is known for its performance and programmability, making it a reliable choice for embedded systems.
Compliance information indicates RoHS3 compliance, MSL 1 Unlimited, and REACH Unaffected status. However, these compliance details are based on existing database information and may require verification.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The device supports 5.0-V in-system programmability.
The package type is QFP.
It provides 600 to 5,000 usable gates.
The pin-to-pin delay is as fast as 5 ns.
The counter speed is up to 175.4 MHz.
Yes, it features 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface.
Yes, it includes built-in JTAG boundary-scan test (BST) circuitry.