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epm7128EQC100-10 The Altera EPM7128EQC100-10 is a high-performance CPLD from the MAX 7000 family. It offers up to 5000 usable gates and fast 5 ns pin-to-pin delays.
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epm7128EQC100-10

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Mfr Name: Altera
Altera
The Altera EPM7128EQC100-10 is a high-performance CPLD from the MAX 7000 family. It offers up to 5000 usable gates and fast 5 ns pin-to-pin delays.
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epm7128EQC100-10 Specifications Quick View

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epm7128EQC100-10 Description

Short technical summary and product information.

The Altera EPM7128EQC100-10 is a Complex Programmable Logic Device (CPLD) belonging to the MAX 7000 family. Based on Altera's second-generation MAX architecture and fabricated with advanced CMOS technology, this EEPROM-based device provides a density of up to 5,000 usable gates. It features in-system programmability (ISP) via an IEEE Std. 1149.1 JTAG interface and offers pin-to-pin delays as fast as 5 ns, with counter speeds reaching up to 175.4 MHz.

 

This CPLD is housed in a QFP package. It supports 5.0-V in-system programmability and includes built-in JTAG boundary-scan test (BST) circuitry. The MAX 7000 family devices, including this model in specific speed grades, comply with PCI Special Interest Group standards.

 

Ideal for various digital logic applications, the EPM7128EQC100-10 combines high performance with the flexibility of in-system programmability. Its features make it suitable for designs requiring fast logic implementation and efficient board space utilization.

epm7128EQC100-10 Quick Information

Product Type: CPLD
Series: MAX 7000
Canonical Name: Altera MAX 7000 EPM7128EQC100-10 CPLD
Subcategory: Complex Programmable Logic Devices

epm7128EQC100-10 Compliance

RoHS Status: RoHS Compliant
Moisture Sensitivity Level (MSL): 1 Unlimited
REACH Status: REACH Unaffected

epm7128EQC100-10 Estimated Pricing

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1+ $0.50 $0.50

Estimated market price range - modelled values for guidance only, not live distributor offers.

epm7128EQC100-10 Features

  • Up to 5000 usable gates density.
  • Fast 5 ns pin-to-pin delay.
  • Supports 5.0-V in-system programmability.
  • Includes IEEE 1149.1 JTAG interface.
  • Packaged in QFP.

epm7128EQC100-10 Applications

  • High-density logic implementation.
  • Digital signal processing.
  • System interface logic.
  • Embedded control applications.

epm7128EQC100-10 FAQs

7 frequently asked questions generated from this part’s specifications.
What is the package type of the EPM7128EQC100-10?

QFP (Quad Flat Package).

How many usable gates does the EPM7128EQC100-10 have?

5000 gates.

What is the maximum pin-to-pin delay?

5 ns.

What is the counter speed?

175.4 MHz.

Does the device support in-system programming?

Yes, it supports 5.0-V in-system programmability (ISP) via the JTAG interface.

Which JTAG standard does the EPM7128EQC100-10 comply with?

IEEE Std. 1149.1.

What is the ISP circuitry compatibility?

IEEE Std. 1532.

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