K4S641632H-TL75
Samsung Electronics
The Samsung Electronics K4S641632H-TL75 is a 64Mbit SDRAM memory component. It features an LVTTL interface and operates at a maximum frequency of 133MHz.
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20 pcs
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20 pcs | On Request | 1 | On Request | On Request | 06+ | On Request | On Request | |
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7 pcs
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7 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Altera EPM7128AETI1007 is a high-density, high-performance CPLD based on Altera's second-generation MAX architecture. Fabricated with advanced CMOS technology, this EEPROM-based device operates with a 3.3-V supply voltage. It provides a density of up to 10,000 usable gates, supporting in-system programmability (ISP) through an IEEE Std. 1149.1 JTAG interface. The EPM7128AETI1007 offers pin-to-pin delays as fast as 4.5 ns and counter speeds up to 227.3 MHz. It is supplied in a TQFP package, suitable for various embedded applications requiring flexible logic implementation.
This CPLD features built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1 and supports the JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71. Enhanced ISP features contribute to faster programming times. The device is pin-compatible with the popular 5.0-V MAX 7000S devices, offering a migration path for existing designs. Its extended temperature range makes it suitable for demanding environments.
| Qty | Low | High |
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| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The operating voltage is 3.3V.
It provides 600 to 10,000 usable gates.
The maximum pin-to-pin delay is 4.5 ns.
The maximum counter speed is 227.3 MHz.
Yes, it supports in-system programming via a JTAG interface.
It is available in a TQFP package.
It supports the JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71.
