| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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1,200 pcs
|
1200 pcs | On Request | 1 | On Request | On Request | 00+ | On Request | On Request | |
|
62 pcs
|
62 pcs | On Request | 1 | On Request | On Request | 2026-02-25 06:16:38 | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Supply Voltage |
The Altera EPM7128AEFC100-7 is a high-density, high-performance CPLD based on Altera's second-generation MAX architecture. Fabricated with advanced CMOS technology, this EEPROM-based device operates with a 3.3-V supply voltage.
Key specifications include a density range of 600 to 10,000 usable gates, in-system programmability (ISP) via a JTAG interface, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. The EPM7128AEFC100-7 is available in a BGA package.
This CPLD supports IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface for in-system programming and boundary-scan testing. It is pin-compatible with the 5.0-V MAX 7000S devices, offering flexibility in design upgrades.
The MAX 7000AE family provides a robust solution for various digital logic applications requiring programmable logic capabilities.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The nominal supply voltage is 3.3V.
It has a range of 600 to 10,000 usable gates.
The maximum pin-to-pin delay is 4.5ns.
The maximum counter speed is 227.3MHz.
It is available in a BGA (Ball Grid Array) package.
It belongs to the MAX 7000AE family.