| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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75 pcs
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75 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Altera EPM7096QC100-3 is a Complex Programmable Logic Device (CPLD) belonging to the MAX 7000 family, based on Altera's second-generation MAX architecture. Fabricated with advanced CMOS technology, this EEPROM-based device provides up to 5,000 usable gates, in-system programmability (ISP), and fast performance characteristics.
Key electrical specifications include pin-to-pin delays as fast as 5 ns and counter speeds up to 175.4 MHz. The device supports 5.0-V in-system programmability through an IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. It also includes built-in JTAG boundary-scan test (BST) circuitry.
The EPM7096QC100-3 is supplied in a QFP package. The MAX 7000 family devices, including this part, are designed for high-density, high-performance applications requiring flexible logic implementation.
| Qty | Low | High |
|---|---|---|
| 1+ | $2.50 | $2.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The pin-to-pin delay is as fast as 5 ns.
The counter speed is up to 175.4 MHz.
Yes, it supports 5.0-V in-system programmability (ISP).
It uses the IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface for ISP.
It is supplied in a QFP package.
The minimum order quantity is 1 piece.