| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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146 pcs
|
146 pcs | On Request | 1 | On Request | On Request | 9743TP/ | On Request | On Request | |
|
5 pcs
|
5 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
|
5 pcs
|
5 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Manufacturer Name | |
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| SVHC Present |
The EPM7064STC100-7 is a Complex Programmable Logic Device (CPLD) from Altera's MAX 7000S family. Based on a second-generation MAX architecture and fabricated with advanced CMOS technology, this EEPROM-based PLD provides 1.25K usable gates and 64 macrocells.
It operates at a frequency of 125MHz with a 5V supply voltage. Key electrical features include a 5ns pin-to-pin delay and a counter speed of up to 175.4 MHz. The device supports 5.0-V in-system programmability (ISP) via an IEEE Std. 1149.1 JTAG interface. Enhanced features include programmable output slew-rate control and fast input setup times.
The EPM7064STC100-7 is available in a 100-pin TQFP package. It offers a programmable power-saving mode for reduced power consumption and a programmable security bit for design protection. The device supports 3.3-V or 5.0-V operation with MultiVolt I/O interface capability, allowing it to interface with both 3.3-V and 5.0-V devices.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
5 V.
TQFP-100.
100 pins.
Yes, it has an IEEE Std. 1149.1 JTAG interface.
Yes, it supports 5.0-V in-system programmability.
5 ns.
175.4 MHz.