| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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5,650 pcs
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5650 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
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5,497 pcs
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5497 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
|
11 pcs
|
11 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Altera EPM7064AETI44-7 is a high-performance, 3.3-V EEPROM-based Programmable Logic Device (PLD) built on the second-generation Multiple Array MatriX (MAX) architecture. This device offers fast operation with pin-to-pin logic delays of 4.5 ns and counter frequencies up to 227.3 MHz.
Featuring a MultiVolt I/O interface, the EPM7064AETI44-7 allows its core to run at 3.3 V while supporting I/O compatibility with 5.0-V, 3.3-V, and 2.5-V logic levels. It supports in-system programmability (ISP) through an IEEE Std. 1149.1 JTAG interface and includes boundary-scan test (BST) circuitry.
This PLD is available in a 44-TQFP package, suitable for surface mount applications. The MAX 7000A family ranges from 600 to 10,000 usable gates, providing high-density solutions for various digital logic needs.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The device core operates at 3.3 V, and its MultiVolt I/O interface is compatible with 2.5 V, 3.3 V, and 5.0 V logic levels.
The EPM7064AETI44-7 is available in a 44-TQFP package.
The device has a pin-to-pin logic delay of 4.5 ns.
The EPM7064AETI44-7 can operate at counter frequencies of up to 227.3 MHz.