LC4032V75TN48C
lat
The Lattice LC4032V75TN48C is a CPLD from the ispMACH 4000V family. It features 32 macrocells and operates at 3.3V with a propagation delay of 7.5ns.
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7,232 pcs
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7232 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Altera EPM7064AET144-7 is a high-density, high-performance CPLD belonging to the MAX 7000A family. Fabricated using advanced CMOS technology, this EEPROM-based device operates with a 3.3-V supply voltage and provides a logic density ranging from 600 to 10,000 usable gates.
Key electrical characteristics include a fast pin-to-pin delay of 4.5 ns and a counter speed of up to 227.3 MHz. The device supports 3.3-V in-system programmability (ISP) via an IEEE 1149.1 (JTAG) interface and includes built-in boundary-scan test (BST) circuitry compliant with IEEE 1149.1. It also supports JEDEC Jam Standard Test and Programming Language (STAPL).
Packaged in a QFP144, the EPM7064AET144-7 is pin-compatible with the 5.0-V MAX 7000S devices. Its architecture includes dedicated inputs for global control signals, making it suitable for various digital logic applications requiring flexible and programmable solutions.
| Qty | Low | High |
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| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The supply voltage is 3.3V.
The package type is QFP144.
The pin-to-pin delay is as fast as 4.5 ns.
The device provides 600 to 10,000 usable gates.
Yes, it supports 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface.
Yes, it is pin-compatible with the popular 5.0-V MAX 7000S devices.
