| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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3,400 pcs
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3400 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Manufacturer Name | |
| Delay Time tpd(1) Max | |
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| Number of Gates | |
| Number of I | |
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| Number of Macrocells | |
| Operating Temperature | |
| Programmable Type | |
| Supplier Device Package | |
| Voltage Supply |
The Intel EPM7064AEFC100-4 is a high-performance, 3.3-V EEPROM-based programmable logic device (PLD) from the MAX 7000A family. Built on the second-generation Multiple Array MatriX (MAX) architecture, this CPLD offers 64 macrocells and a fast 4.5ns pin-to-pin logic delay, enabling counter frequencies up to 227.3 MHz. It features a MultiVoltTM I/O interface, allowing the core to run at 3.3V while supporting 5.0-V, 3.3-V, and 2.5-V logic levels on its I/O pins.
Designed for in-system programmability (ISP) via an IEEE Std. 1149.1 JTAG interface, the EPM7064AEFC100-4 also includes boundary-scan test (BST) circuitry. It supports JEDEC Jam Standard Test and Programming Language (STAPL) and is PCI-compatible with a bus-friendly architecture. The device is available in a 100-FBGA (11x11) package, suitable for surface mounting.
With 1250 gates and 68 I/O pins, this CPLD is suitable for various embedded applications requiring flexible logic implementation. It operates within a temperature range of 0°C to 70°C (TA) and is designed for 3V to 3.6V supply voltage.
The maximum pin-to-pin logic delay is 4.5 ns.
The device features 64 macrocells.
The voltage supply range is 3V to 3.6V.
The operating temperature range is 0°C to 70°C (TA).
It is supplied in a 100-FBGA (11x11) package.
Yes, it supports in-system programmability through its JTAG interface.