| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
5 pcs
|
5 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| AEC Qualified | |
| Automotive Grade | |
| Industrial Grade | |
| Medical Grade | |
| Military Grade | |
| Storage Temperature | |
| Tape & Reel |
The Altera EPM5130GM is part of the MAX 5000 family of Erasable Programmable Logic Devices (EPLDs). These devices utilize CMOS EPROM cells for configuring logic functions, offering flexibility for design iterations. The EPM5130GM provides a high-speed, high-density replacement for SSI and MSI TTL/CMOS packages and conventional PLDs.
Key technical specifications include a maximum counter frequency of 100 MHz, a pipelined data rate of 100 MHz, and a combinatorial delay of 15 ns. It supports system clock rates up to 66 MHz. The device architecture offers 16 to 192 macrocells and 32 to 384 flip-flops, with pin counts ranging from 20 to 100.
This CPLD is manufactured using an advanced 0.8-micron CMOS EPROM technology. It is available in a PGA-100 package. The MAX 5000 architecture is designed to solve speed, density, and design flexibility challenges, making it suitable for integrating complete subsystems into a single package, thereby saving board area and reducing power consumption.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The maximum counter frequency for the EPM5130GM is 100 MHz.
The pipelined data rate of the EPM5130GM is 100 MHz.
The combinatorial delay for the EPM5130GM is 15 ns.
The EPM5130GM comes in a PGA-100 package.
The EPM5130GM is RoHS3 Compliant.
The Moisture Sensitivity Level (MSL) for the EPM5130GM is 1 Unlimited.