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62 pcs
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62 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Altera EPM5128JC-2 is an Erasable Programmable Logic Device (EPLD) from the MAX 5000 family. It represents a significant advancement in programmable logic, combining an innovative architecture with a state-of-the-art process to deliver optimal performance, logic density, and flexibility.
This EPLD is designed as a high-speed, high-density replacement for SSI and MSI TTL and CMOS packages, as well as conventional PLDs. It offers a 15-ns combinatorial delay, counter frequencies up to 100 MHz, and pipelined data rates of 100 MHz. For complex designs, it supports true system clock rates up to 66 MHz.
The EPM5128JC-2 is available in a PLCC68 package, suitable for surface mount applications. Its architecture is based on the MAX 5000, which merges the speed and ease of use of PAL devices with the density of programmable gate arrays. Development tools like MAX+PLUS and MAX+PLUS II are available for compiling designs.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The combinatorial delay is 15 ns.
The maximum counter frequency is 100 MHz.
The pipelined data rate is 100 MHz.
The maximum system clock rate is 66 MHz.
The EPM5128JC-2 is available in a PLCC68 package.