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23 pcs
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23 pcs | On Request | 1 | On Request | On Request | 9431 | On Request | On Request | |
| On Request | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| SVHC Present |
The Altera EPM5128GC-1 is a Complex Programmable Logic Device (CPLD) belonging to the MAX 5000 series. It features an architecture that combines the speed and ease of use of PAL devices with the density of programmable gate arrays.
Key electrical specifications include 2.5K logic gates and 128 macro cells. The device operates at 5V and offers a maximum combinatorial delay of 15 ns. It supports counter frequencies up to 100 MHz, pipelined data rates of 100 MHz, and system clock rates up to 66 MHz.
This CPLD is designed as a high-speed, high-density replacement for SSI and MSI TTL and CMOS packages, as well as conventional PLDs. It is available in a PGA-68 package, suitable for various electronic designs requiring flexible logic implementation.
The MAX 5000 series CPLDs are supported by MAX+PLUS and MAX+PLUS II development tools, facilitating the compilation of large designs efficiently. An industry-standard EDIF interface is also available for integration with third-party CAE tools.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The EPM5128GC-1 operates at 5V.
The EPM5128GC-1 is available in a PGA-68 package.
The EPM5128GC-1 is RoHS3 Compliant.
The MSL for the EPM5128GC-1 is 1 Unlimited.
The EPM5128GC-1 has counter frequencies up to 100 MHz and pipelined data rates of 100 MHz, with system clock rates up to 66 MHz.
The EPM5128GC-1 has 128 macro cells.
The EPM5128GC-1 has 2.5K gates.