| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
2 pcs
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2 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Manufacturer Name | |
| Storage Temperature | |
| Tape & Reel |
The Altera EPM5032JC-25 is an Erasable Programmable Logic Device (EPLD) from the MAX 5000 series. It combines an innovative architecture with advanced process technology to deliver high performance, logic density, and flexibility for general-purpose reprogrammable logic applications.
This EPLD functions as a high-speed, high-density replacement for SSI and MSI TTL and CMOS packages, as well as conventional PLDs. It features a combinatorial delay of 15 ns, a counter frequency of up to 100 MHz, and pipelined data rates of 100 MHz. For complex designs, it supports true system clock rates up to 66 MHz.
The EPM5032JC-25 is available in a PLCC package. Development tools like MAX+PLUS and MAX+PLUS II are available for compiling designs, and an EDIF interface supports third-party CAE tools.
This part is listed as obsolete and is available as factory excess stock or from franchised distributors.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The combinatorial delay is 15 ns.
The maximum counter frequency is 100 MHz.
The pipelined data rate is 100 MHz.
The system clock rate is up to 66 MHz.
The EPM5032JC-25 is available in a PLCC package.
The RoHS status is RoHS3 Compliant.
The MSL is 1 Unlimited.