| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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12 pcs
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12 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
|
5 pcs
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5 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| SVHC Present |
The Altera EPM5032DC-25 is an Erasable Programmable Logic Device (EPLD) from the MAX 5000 family. It is designed as a high-speed, high-density replacement for SSI and MSI TTL and CMOS packages, as well as conventional PLDs. This device combines an advanced architecture for speed and ease of use, similar to PAL devices but with the density of programmable gate arrays.
Key technical specifications include a typical combinatorial delay of 15 ns, counter frequencies up to 100 MHz, and pipelined data rates of 100 MHz. For complex designs, it supports true system clock rates up to 66 MHz. The device is described as a UV PLD, PAL-Type, CMOS, CDIP28, windowed, ceramic, DIP-28.
This EPLD is available in a DIP-28 package. It is noted as obsolete with stock resources from factory excess or franchised distributors. Development tools like MAX+PLUS and MAX+PLUS II are available for design compilation.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The typical combinatorial delay is 15 ns.
The counter frequency is up to 100 MHz.
The pipelined data rate is up to 100 MHz.
The true system clock rate for high-complexity designs is up to 66 MHz.
The EPM5032DC-25 is available in a DIP-28 package.
The RoHS status is RoHS3 Compliant.
The Moisture Sensitivity Level (MSL) is 1 Unlimited.