| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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17,219 pcs
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17219 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Altera EPM3032A is a member of the MAX 3000A family of programmable logic devices. Built on a Multiple Array MatriX (MAX) architecture, this CPLD provides 600 usable gates and 32 macrocells.
Key electrical specifications include a fast 4.5ns pin-to-pin logic delay and a maximum counter frequency of 192.3 MHz. The device supports a 3.3V core voltage with MultiVolt I/O, allowing compatibility with 5.0V, 3.3V, and 2.5V logic levels. It also features 3.3V in-system programmability (ISP) via an IEEE 1149.1 JTAG interface.
The EPM3032A is available in various packages including Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), and Plastic J-Lead Chip Carrier (PLCC). Its bus-friendly architecture includes programmable slew-rate control and an open-drain output option, making it suitable for a range of embedded applications.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The core operates at 3.3 V. The I/O interface is compatible with 5.0 V, 3.3 V, and 2.5 V logic levels.
The EPM3032A is available in 44-pin TQFP, PQFP, and PLCC packages.
The maximum propagation delay is 4.5 ns.
It has 32 macrocells and 600 usable gates.
The maximum counter frequency is 192.3 MHz.
The maximum setup time is 3.0 ns.
The I/O pins are compatible with 5.0 V, 3.3 V, and 2.5 V logic levels.