EPC2TI32

The Intel EPC2TI32 is an in-system programmable, high-density, high-performance EPLD based on Altera's third-generation MAX architecture. Fabricated on advanced CMOS technology, it provides 6,000 to 12,000 usable gates, with pin-to-pin delays as fast as 10 ns and counter speeds up to 144 MHz.

This device supports 5.0-V in-system programmability (ISP) via a built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. It operates with a supply voltage range of 3V to 5.5V and has a memory size of 1.6 Mbit. The operating temperature ranges from -40°C to 85°C.

The EPC2TI32 is housed in a 32-TQFP package and is suitable for surface mount applications. It is fully compliant with the Peripheral Component Interconnect Special Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2.

Key features include a dual-output macrocell for independent use of combinatorial and registered logic, FastTrack® Interconnect for fast, predictable interconnect delays, and input/output registers with clear and clock enable on all I/O pins. It also offers programmable output slew-rate control to reduce switching noise and MultiVolt™ I/O interface operation.