| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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1 pcs
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1 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Mounting Type | |
| SVHC Present |
The Altera EP910LC30 is part of the Classic EPLD family, designed for high-speed, low-power logic integration. Fabricated on advanced CMOS technology, this device supports 100% TTL emulation and can integrate multiple PAL- and GAL-type devices. It features combinatorial speeds as fast as 10 ns and counter frequencies up to 100 MHz.
The EP910LC30 offers a programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins. Macrocells are individually programmable as D, T, JK, or SR flip-flops, or for combinatorial operation. The device is available in a PLCC44 package, suitable for surface mount applications.
This EPLD family provides densities ranging from 300 to 900 usable gates. EPROM-based Classic devices can reduce active power consumption without sacrificing performance, making them well-suited for low-power applications. Devices are generically tested and can be erased with UV light for quick design changes.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
16 macroells.
10 ns maximum.
100 MHz.
125 MHz.
Between 300 and 900 usable gates.
PLCC44 (surface-mount).
Altera EP910LC-30 is a direct replacement.
