EP910DI35

The Altera EP910DI35 is a high-performance, 16-macrocell Classic EPLD CPLD fabricated on advanced CMOS technology. It offers a solution for high-speed, low-power logic integration, supporting 100% TTL emulation and integrating multiple PAL- and GAL-type devices. With densities ranging from 300 to 900 usable gates, this device provides pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz.

Key features include a programmable I/O architecture supporting up to 20 inputs or 16 outputs and 2 clock pins. Macrocells are individually programmable as D, T, JK, or SR flipflops, or for combinatorial operation. The EP910DI-35 is available in a 40-pin CDIP package. EPROM-based Classic devices can reduce active power consumption without sacrificing performance, making them suitable for a wide range of low-power applications. These devices are 100% generically tested and can be erased with UV light for quick design changes.

This obsolete part is available as factory excess stock or from franchised distributors. It is suitable for applications requiring logic integration and high-speed performance.