| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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74 pcs
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74 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request | |
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1 pcs
|
1 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Altera EP610PC-25 is a device from the Classic EPLD family, designed for high-speed, low-power logic integration. Fabricated on advanced CMOS technology, this CPLD offers 16 macrocells and approximately 300 usable gates, supporting TTL emulation. It operates at a frequency of up to 40MHz with a logic delay as low as 10ns, powered by a 5V supply.
The EP610PC-25 comes in a 24-pin PDIP package, suitable for through-hole mounting. It includes 4 dedicated input pins and 16 I/O pins, along with 2 global clock pins. The device utilizes sum-of-products logic with a programmable register, allowing for flexible D, T, SR, or JK flip-flop configurations, or bypass for combinatorial operation. Macrocell registers can be clocked by a global clock or feedback paths.
This CPLD is well-suited for applications requiring logic integration and is supported by Altera's MAX+PLUS II development system. Its EPROM-based nature allows for UV light erasure, facilitating quick design changes.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.99 | $0.99 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The EP610PC-25 operates at a voltage of 5V.
The EP610PC-25 is available in a 24-pin PDIP package.
The RoHS status is No.
The MSL is 1.