| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
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20 pcs
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20 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Altera EP610LC35 is a CPLD belonging to the Classic EPLD family, designed for high-speed, low-power logic integration. Fabricated on advanced CMOS technology, this device offers 300 usable gates and 16 macrocells.
Key electrical specifications include an operating voltage of 5V and a maximum operating frequency of 28.6MHz. The device supports TTL emulation and can integrate multiple PAL- and GAL-type devices. It provides pin-to-pin logic delays as low as 10 ns and counter frequencies up to 100 MHz.
The EP610LC35 is available in a 28-pin PLCC package, suitable for surface mounting. Classic devices are EPROM-based, allowing for erasure with UV light for quick design changes. They utilize sum-of-products logic with a programmable register that can be configured for D, T, SR, or JK flipflop operation, or bypassed for combinatorial logic.
This CPLD is well-suited for a wide range of low-power applications due to its reduced active power consumption without sacrificing performance. It is supported by Altera’s MAX+PLUS II development system.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
5 V.
PLCC-28 surface mount.
16 macro cells.
300 gates.
28.6 MHz.
10 ns.
100 MHz.