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1 pcs
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1 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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The Intel EP610LC-25 is a 16-macrocell Classic EPLD designed for high-performance applications. It features combinatorial speeds with a propagation delay (tPD) as low as 10 ns and can achieve counter frequencies of up to 100 MHz. The device supports pipelined data rates also up to 100 MHz.
With a programmable I/O architecture, it can accommodate up to 20 inputs or 16 outputs, along with 2 clock pins. The macrocells are individually programmable as D, T, JK, or SR flip-flops, or for combinatorial operation. This EPLD is available in multiple package options, including a 24-pin small-outline integrated circuit (SOIC), a 24-pin dual in-line package (DIP), and a 28-pin plastic J-lead chip carrier (PLCC).
This device is pin-, function-, and programming file-compatible with other devices such as EP610, EP610I, EP610T, EP610-XX/B, EP600I, and PALCE610. It also offers a programmable clock option for independent clocking of all registers.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The minimum propagation delay (tPD) for combinatorial logic is 10 ns.
The maximum counter frequency is 100 MHz.
The EP610LC-25 features 16 macrocells.
The EP610LC-25 is available in 24-pin SOIC, 24-pin DIP, and 28-pin PLCC packages.