EP610DI35 Altera EP610DI35 is a CPLD with 16 macrocells and 16 I/O pins. It features a 10 ns pin-to-pin logic delay and operates at counter frequencies up to 100 MHz.
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EP610DI35

Available from 1 distributors
Mfr Name: Altera
Altera
Altera EP610DI35 is a CPLD with 16 macrocells and 16 I/O pins. It features a 10 ns pin-to-pin logic delay and operates at counter frequencies up to 100 MHz.
✓ Total Stock: 1 pcs
$ Price Range: $0.50

EP610DI35 Available from 1 distributor

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EP610DI35 Specifications Quick View

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EP610DI35 Description

Short technical summary and product information.

The Altera EP610DI35 is a Complex Programmable Logic Device (CPLD) featuring 16 macrocells and 16 I/O pins. It provides 4 dedicated input pins and 2 global clock pins for flexible logic implementation. The device offers a minimum pin-to-pin logic delay of 10 ns and supports counter frequencies up to 100 MHz, making it suitable for high-speed control and glue logic applications.

 

The EP610DI35 is housed in a CDIP24 package, which is a ceramic dual in-line package with 24 pins. This package is suitable for through-hole mounting on printed circuit boards. The device is designed for use in a variety of embedded systems requiring programmable logic with moderate density.

 

Key specifications include 16 macrocells, 16 I/O pins, 4 dedicated inputs, and 2 global clocks. The logic delay is as low as 10 ns, and the maximum counter frequency is 100 MHz. Compliance data indicates RoHS3, REACH unaffected, and MSL 1 status, though these are unverified.

EP610DI35 Quick Information

Product Type: CPLD (Complex Programmable Logic Device)
Series: EP610
Canonical Name: Altera EP610DI35 CPLD
Subcategory: Complex Programmable Logic Devices

EP610DI35 Compliance

RoHS Status: RoHS Compliant
Moisture Sensitivity Level (MSL): 1 Unlimited
REACH Status: REACH Unaffected

EP610DI35 Estimated Pricing

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1+ $0.50 $0.50

Estimated market price range - modelled values for guidance only, not live distributor offers.

EP610DI35 Features

  • 16 macrocells for logic implementation.
  • 16 I/O pins for external connections.
  • 10 ns minimum pin-to-pin logic delay.
  • 100 MHz maximum counter frequency.
  • CDIP24 package for through-hole mounting.

EP610DI35 Applications

  • High-speed logic integration for embedded systems
  • TTL emulation replacing multiple PAL devices
  • Low-power logic for portable equipment
  • Programmable control in industrial automation
  • Clock distribution in timing applications

EP610DI35 FAQs

6 frequently asked questions generated from this part’s specifications.
What is the package type of the EP610DI35?

The EP610DI35 is available in a CDIP24 package.

How many macrocells does the EP610DI35 have?

The EP610DI35 has 16 macrocells.

What is the pin-to-pin logic delay of the EP610DI35?

The minimum pin-to-pin logic delay is 10 ns.

What is the maximum counter frequency of the EP610DI35?

The maximum counter frequency is 100 MHz.

How many I/O pins does the EP610DI35 have?

The EP610DI35 has 16 I/O pins.

How many dedicated input pins and global clock pins are available?

The device has 4 dedicated input pins and 2 global clock pins.

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