| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
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1 pcs
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1 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
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| Manufacturer Name | |
| SVHC Present |
The Altera EP610DI35 is a Complex Programmable Logic Device (CPLD) featuring 16 macrocells and 16 I/O pins. It provides 4 dedicated input pins and 2 global clock pins for flexible logic implementation. The device offers a minimum pin-to-pin logic delay of 10 ns and supports counter frequencies up to 100 MHz, making it suitable for high-speed control and glue logic applications.
The EP610DI35 is housed in a CDIP24 package, which is a ceramic dual in-line package with 24 pins. This package is suitable for through-hole mounting on printed circuit boards. The device is designed for use in a variety of embedded systems requiring programmable logic with moderate density.
Key specifications include 16 macrocells, 16 I/O pins, 4 dedicated inputs, and 2 global clocks. The logic delay is as low as 10 ns, and the maximum counter frequency is 100 MHz. Compliance data indicates RoHS3, REACH unaffected, and MSL 1 status, though these are unverified.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The EP610DI35 is available in a CDIP24 package.
The EP610DI35 has 16 macrocells.
The minimum pin-to-pin logic delay is 10 ns.
The maximum counter frequency is 100 MHz.
The EP610DI35 has 16 I/O pins.
The device has 4 dedicated input pins and 2 global clock pins.