Mfr Part #:

EP2S15F484C5

Mfr Name: Altera

The Altera Stratix II FPGA EP2S15F484C5 is a high-performance FPGA based on a 1.2-V, 90-nm process. It offers advanced features for demanding applications.

✓ Total Stock: 7 pcs

$ Price Range: $22.15

EP2S15F484C5 Available from 1 distributor

✓ Authorised

✓ Non-Authorised

Distributor		Stock	Pricing	MOQ	PKG	Lead Time	Date Code	On Order Quantity	On Order Delivery
Bristol Electronics ✓ Non-Authorised Inventory information	7 pcs On Request	7 pcs	On Request	1	On Request	On Request	On Request	On Request	On Request

EP2S15F484C5 Specifications Quick View

Most important parameters for selection – full specs in datasheet.

SELECT ALL

Category	New Products
Manufacturer Name	Altera
Clock Frequency	Up to 550 MHz
Lead Style	Bga
Operating Voltage	1.2 V
SVHC Present	Not Present

View Similar Products (0)

EP2S15F484C5 Description

Short technical summary and product information.

The Altera Stratix II FPGA family, including the EP2S15F484C5, is built on a 1.2-V, 90-nm all-layer copper SRAM process. This family features a new logic structure designed to maximize performance and achieve device densities approaching 180,000 equivalent logic elements (LEs).

Stratix II devices provide substantial on-chip memory, offering up to 9 Mbits of TriMatrix memory for memory-intensive applications. They also include up to 96 DSP blocks with numerous multipliers for efficient implementation of digital signal processing functions. Various high-speed external memory interfaces are supported, including DDR SDRAM, DDR2 SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM.

These FPGAs support diverse I/O standards and offer 1-gigabit per second (Gbps) source synchronous signaling with DPA circuitry. The clock management solution includes internal clock frequencies up to 550 MHz and up to 12 phase-locked loops (PLLs). Notably, Stratix II devices are the first FPGAs capable of decrypting configuration bitstreams using the Advanced Encryption Standard (AES) algorithm, enhancing design protection.

EP2S15F484C5 Quick Information

Product Type: FPGA

Series: Stratix II

Canonical Name: Altera Stratix II FPGA EP2S15F484C5

Subcategory: Field Programmable Gate Array

EP2S15F484C5 Compliance

RoHS Status: RoHS Compliant

Moisture Sensitivity Level (MSL): 1 Unlimited

REACH Status: REACH Unaffected

EP2S15F484C5 Estimated Pricing

Qty	Low	High
1+	$22.15	$22.15

Estimated market price range - modelled values for guidance only, not live distributor offers.

EP2S15F484C5 Features

Up to 180,000 equivalent logic elements.
Up to 9 Mbits of on-chip TriMatrix memory.
Supports multiple high-speed memory interfaces.
Internal clock frequency up to 550 MHz.
AES bitstream decryption for design protection.

EP2S15F484C5 Applications

Suitable for memory-intensive applications.
Efficient implementation of DSP functions.
Supports high-speed data signaling.
Provides robust clock management solutions.

EP2S15F484C5 FAQs

7 frequently asked questions generated from this part’s specifications.

What is the logic element density of the Altera Stratix II FPGA?

The Stratix II FPGA family enables device densities approaching 180,000 equivalent logic elements (LEs).

How much on-chip memory does the Stratix II FPGA offer?

Stratix II devices offer up to 9 Mbits of on-chip TriMatrix memory.

What DSP capabilities does the Stratix II FPGA have?

Stratix II devices have up to 96 DSP blocks with up to 384 multipliers.

Which external memory interfaces are supported by the Stratix II FPGA?

Supported interfaces include DDR SDRAM, DDR2 SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM.

What is the maximum internal clock frequency for Stratix II FPGAs?

Stratix II devices offer an internal clock frequency of up to 550 MHz.

Does the Stratix II FPGA support AES encryption?

Yes, Stratix II devices are the industry’s first FPGAs with the ability to decrypt a configuration bitstream using the Advanced Encryption Standard (AES) algorithm.

What is the operating voltage for the Stratix II FPGA family?

The Stratix II FPGA family is based on a 1.2-V process.