| Distributor | Stock | Pricing | MOQ | PKG | Lead Time | Date Code | On Order Quantity | On Order Delivery | |
|---|---|---|---|---|---|---|---|---|---|
|
2,005 pcs
|
2005 pcs | On Request | 1 | On Request | On Request | 24+ | On Request | On Request | |
|
1,067 pcs
|
1067 pcs | On Request | 1 | On Request | On Request | 17+ | On Request | On Request | |
|
37 pcs
|
37 pcs | On Request | 1 | On Request | On Request | On Request | On Request | On Request |
| Category | |
| Manufacturer Name | |
| Storage Temperature | |
| Tape & Reel |
The Altera EP1K50TC144-3N is part of the ACEX 1K family of programmable logic devices (PLDs), designed for high-volume applications requiring system-on-a-programmable-chip (SOPC) integration. This device features a high density architecture with 50,000 typical gates and up to 199,000 maximum system gates. It includes 2,880 logic elements (LEs) and 10 embedded array blocks (EABs) providing a total of 40,960 RAM bits.
System-level features include MultiVoltTM I/O pins that can interface with 2.5-V, 3.3-V, or 5.0-V devices, offering significant design flexibility. The device supports bidirectional I/O performance up to 250 MHz and is compliant with the PCI Local Bus Specification Revision 2.2 for both 3.3-V and 5.0-V operation. It also incorporates JTAG boundary-scan test circuitry compliant with IEEE Std. 1149.1-1990.
The ACEX 1K family utilizes a cost-optimized process and a flexible interconnect structure for fast, predictable routing delays. The EP1K50TC144-3N is supplied in a 144-TQFP package, suitable for surface mounting.
| Qty | Low | High |
|---|---|---|
| 1+ | $0.50 | $0.50 |
Estimated market price range - modelled values for guidance only, not live distributor offers.
The typical gate count is 50,000 gates.
It has 2,880 logic elements.
The maximum number of user I/O pins is 249.
It is packaged in a 144-TQFP package.
The internal supply voltage is 2.5 V.
Yes, it complies with Revision 2.2 for 3.3 V and 5.0 V operation.